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this is information on a product in full production. october 2014 docid026330 rev 2 1/14 STL11N65M5 n-channel 650 v, 0.475 ? typ., 8.5 a mdmesh? m5 power mosfet in a powerflat? 5x5 package datasheet - production data figure 1. internal schematic diagrams features ? extremely low r ds(on) ? low gate charge and input capacitance ? excellent switching performance ? 100% avalanche tested applications ? switching applications description this device is an n-channel power mosfet based on mdmesh? m5 innovative vertical process technology combined with the well- known powermesh? horizontal layout. the resulting product offers extremely low on- resistance, making it particularly suitable for applications requiring high power and superior efficiency. powerflat 5x5 tm 1 4 12 7 6 5 11 10 am15540v5 top view d(5, 6, 11, 12) g(10) s(2, 3, 4, 7, 8, 9) g 10 s 9 s 8 s 7 1 nc 2 s 3 s 4 s 6 d 5 d d 11 d 12 pin 1 identification order code v ds @ t j max. r ds(on) max i d STL11N65M5 710 v 0.530 ? 8.5 a table 1. device summary order code marking package packaging STL11N65M5 11n65m5 powerflat ? 5x5 tape and reel www.st.com
contents STL11N65M5 2/14 docid026330 rev 2 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
docid026330 rev 2 3/14 STL11N65M5 electrical ratings 14 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 650 v v gs gate-source voltage 25 v i d (1) 1. limited by maximum junction temperature drain current (continuous) at t c = 25 c 8.5 a i d (1) drain current (continuous) at t c = 100 c 4.9 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 34 a i d (3) 3. when mounted on fr-4 board of 1 inch2, 2 oz cu (t < 100 s) drain current (continuous) at t pcb =25c 1.35 a i d(3) drain current (continuous) at t pcb =100c 0.86 a i dm(2),(3) drain current (pulsed) 5.4 a p tot (1) total dissipation at t c = 25 c 70 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 1.9 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 130 mj dv/dt (4) 4. i sd 8.5 a, di/dt 400 a/s, v peak v (br)dss , v dd = 400 v. peak diode recovery voltage slope 15 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 1.78 c/w r thj-pcb (1) 1. when mounted on 1inch2 fr-4 board, 2 oz cu, t<100 sec thermal resistance junction-pcb max 58.5 c/w
electrical characteristics STL11N65M5 4/14 docid026330 rev 2 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 1 ma 650 v i dss zero gate voltage drain current (v gs = 0) v ds = 650 v 1 a v ds = 650 v, t c =125 c 100 a i gss gate-body leakage current (v ds = 0) v gs = 25 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 3 4 5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 4.25 a 0.475 0.530 ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 -644-pf c oss output capacitance - 18 - pf c rss reverse transfer capacitance -2.5-pf c o(tr) (1) 1. c oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 520 v, v gs = 0 -55-pf c o(er) (2) 2. c oss eq. energy related is defined as a constant equival ent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related -17-pf r g intrinsic gate resistance f = 1 mhz open drain - 5 - ? q g total gate charge v dd = 520 v, i d = 4.5 a, v gs = 10 v (see figure 16 ) -17-nc q gs gate-source charge - 4.6 - nc q gd gate-drain charge - 8.5 - nc
docid026330 rev 2 5/14 STL11N65M5 electrical characteristics 14 table 7. source drain diode table 6. switching times symbol parameter test conditions min. typ. max unit t d (v) voltage delay time v dd = 400 v, i d = 6 a, r g = 4.7 ? , v gs = 10 v (see figure 17 ), (see figure 20 ) -23-ns t r(v) voltage rise time - 10 - ns t f(i) current fall time - 13.5 - ns t c(off) crossing time - 13 - ns symbol parameter test conditions min. typ. max. unit i sd (1) source-drain current - 8.5 a i sdm (1) , (2) 1. limited by maximum junction temperature 2. pulse width limited by safe operating area source-drain current (pulsed) - 34 a v sd (3) 3. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 8.5 a, v gs = 0 - 1.5 v t rr reverse recovery time i sd = 8.5 a, di/dt = 100 a/s v dd = 60 v (see figure 17 ) -232 ns q rr reverse recovery charge - 2 c i rrm reverse recovery current - 17.5 a t rr reverse recovery time i sd = 8.5 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 17 ) -328 ns q rr reverse recovery charge - 2.8 c i rrm reverse recovery current - 17 a
electrical characteristics STL11N65M5 6/14 docid026330 rev 2 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. static drain-source on-resistance figure 7. gate charge vs gate-source voltage , ' 9 '6 9 $ 2shudwlrqlqwklvduhdlv /lplwhge\pd[5 '6rq pv 7m ?& 7sfe ?& 6lqjohsxovh v pv *,3*6$ i d 6 4 2 0 0 10 v ds (v) 20 (a) 5 15 25 v gs =9, 10v 8 6v 7v 8v 10 12 14 16 am15897v1 i d 6 4 2 0 3 5 v ds (v) 7 (a) 4 6 8 v ds =25v 9 8 10 12 14 16 am15898v1 r ds(on) 0.475 0.45 0.425 0.4 0 7 i d (a) ( ) 3 0.5 0.525 2 5 8 1 46 0.55 0.575 v gs =10 v am15899v1 v gs 6 4 2 0 0 5 q g (nc) (v) 20 8 10 15 10 v dd =520v i d =4.5a 12 300 200 100 0 400 500 v ds v ds (v) am15900v1
docid026330 rev 2 7/14 STL11N65M5 electrical characteristics 14 figure 8. capacitance variations figure 9. output capacitance stored energy figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature figure 12. source-drain diode forward characteristics figure 13. normalized v (br)dss vs temperature c 1000 100 10 1 0.1 1 v ds (v) (pf) 10 ciss coss crss 100 am15903v1 e oss 1 0.5 0 0 100 v ds (v) (j) 400 1.5 200 300 2 2.5 500 600 3 3.5 am15901v1 v gs(th) 1.00 0.90 0.80 0.70 -50 0 t j (c) (norm) -25 1.10 75 25 50 100 i d = 250 a v ds = v gs am05459v1 r ds(on) 1.7 1.3 0.9 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 0.7 1.1 1.5 1.9 2.1 v gs = 10v i d = 4.25 a am05460v1 v sd 0 20 i sd (a) (v) 10 50 30 40 0 0.2 0.4 0.6 0.8 1.0 1.2 t j =-50c t j =150c t j =25c am05461v1 9 %5'66 7 - ?& qrup , ' p$ $0y
electrical characteristics STL11N65M5 8/14 docid026330 rev 2 figure 14. switching losses vs gate resistance (1) 1. eon including reverse recovery of a sic diode e 0 0 20 r g ( ) ( j) 10 30 20 40 40 i d =6a v dd =400v eon eoff 60 v gs =10v 80 100 am15902v1
docid026330 rev 2 9/14 STL11N65M5 test circuits 14 3 test circuits figure 15. switching times test circuit for resistive load figure 16. gate charge test circuit figure 17. test circuit for inductive load switching and diode recovery times figure 18. unclamped inductive load test circuit figure 19. unclamped inductive waveform figure 20. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am05540v2 id vgs vds 90%vds 10%id 90%vgs on tdelay-off tfall trise tcross -over 10%vds 90%id vgs(i(t)) on -off tfall trise - )) concept waveform for inductive load turn-off
package mechanical data STL11N65M5 10/14 docid026330 rev 2 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid026330 rev 2 11/14 STL11N65M5 package mechanical data 14 figure 21. powerflat? 5x5 type s mechanical drawing 7 10 4 1 8365434_a_type_s 10 9 8 7 1234 6 5 11 12 pin 1 identification
package mechanical data STL11N65M5 12/14 docid026330 rev 2 figure 22. powerflat? 5x5 type s recommended footprint (dimensions are in mm) table 8. powerflat? 5x5 type s mechanical dimensions dim. mm min. typ. max. a 0.80 1.0 a1 0.02 0.05 a2 0.25 b0.30 0.50 d5.00 d1 4.05 4.25 e5.00 e1 0.64 0.79 e2 2.25 2.45 e1.27 l0.45 0.75 8365434_a
docid026330 rev 2 13/14 STL11N65M5 revision history 14 5 revision history table 9. document revision history date revision changes 09-may-2014 1 first release 29-sep-2014 2 updated title, features and description in cover page. document status promoted from preliminary to production data.
STL11N65M5 14/14 docid026330 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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